It is assumed
that the following course material is being made available to
students of SUNY at
They are meant for instructional use only.
|
Date |
Topic |
|
Notes/comments |
|
8/26 |
Introduction to CSE241: Policies and
protocols |
First day handout |
|
| 8/28 |
Foundations of Digital Systems: number
systems: decimal, binary, any radix, radix conversion; |
Ch. 1: up to 1.4 |
|
| 8/30 |
Signed numbers; sign-magnitude; radix-complement; arithmetic;sig-mag representation, 1's, 2's complement, binary arithmetic: addition, subtraction: sig-mag and 2's complement arithemetic | 1.5, 1.6 |
Homework#1 (will be) assigned |
| 9/4 |
Binary code; error correcting codes
etc. Binary storage, processing; Block diagram of
modern digital computer |
1.7, 1.8 |
|
| 9/6 |
Binary logic operations; truth table;
introduction to logic gates |
1.9 |
|
| 9/9 |
Boolean algebra: common
postulates; axioms; two-valued Boolean Algebra, truth
tables |
2.1-2.3 |
Homework#1 Due Homework#2 assigned |
| 9/11 |
Basic theorems and
preoperties; operator precedence; Booleans functions;
realization of Booleans function using logic gates: logic
gates |
2.4-2.5 |
|
| 9/13 |
Algebraic simplification;
canonical and standard forms; minterms and maxterms; sum
of minterms; logic gates; integrated circuits; VLSI
circuits (just breif intro) |
2.6-2.9 |
|
| 9/16 |
Contd. |
||
| 9/18 |
Given a word problem,
describe the function using truth table, obtain
expression, simplify and implement using only NAND gates |
Chapter 2 |
Hwk#3 assigned |
| 9/20 |
gate level minimization:
Karnuagh Map method (K-map) |
3.1-3.5 |
|
| 9/25 |
K-map simplificationw with dont care
conditions; xor function |
3.5, 3.8 |
|
| 9/27 |
A gentle intro to Verilog
HDL |
VHDL |
|
| 9/30 |
Logic circuit analysis;
MSI circuits |
4.1-4.3 |
|
| 10/2 |
Half-adder and
Full-adder; overflow |
4.4-4.6 |
|
| 10/4 |
Excess-3 generator,
magnitude comparator; decoders;priority encoder; tri-state
gates |
4.8-4.11 |
|
| 10/9 |
Review for exam 1 |
Review |
|
| 10/13 |
Gate level modeling Verilog HDL |
4.12 |
|
| 10/16 |
****8AM -
9.50AM****Midterm exam |
See review |
121 Cooke |
| 10/21 |
Introduction to
sequential logic: basic concept; storage elements: latch
and FF; characteristic tables and characteristic
equations; |
Ch. 5:5.1-5.4 |
Hwk#6 assigned |
| 10/23 |
State table, state
diagram and state equations; Introduction to Verilog; gate
level modeling |
Ch 5: 5.5, Ch.4: 4.12 |
|
| 10/25 |
Design and implementation
of seqeuntial circuits |
5.5 (contd.) |
|
| 10/28 |
Still working on the above topics: FF and
Seq Ckts Analysis |
Hwk#7 assigned (different than before) |
|
| 11/4 |
Verilog synthesis as in Section 4.12 |
demos |
|
| 11/8 |
Verilog Synthesis of sequential logic/state
diagram |
(continue) |
Helpful link from
Carl Helpful handout from your TA Jinghao |
| 11/11 |
Sequential logic synthesis: from word
problem to FF circuit |
||
| 11/13 |
Seqeuntion circuit design: this will help
in Hwk#9; we are already done with material for hwk#7 and
Hwk#8 |
Helpful links for behavioral model hwk#7:
|
|
| Helpful
links from JD for many MTH/CSE courses |
|||
| 11/18 |
We worked on Exercise 5.18: Sequential
circuit design using JK-FF (and befre that T-FF) |
||
| 11/21 |
We will work on a counter design |
||
| 12/1-6 |
Final Review |
Final Review |
| Homework# |
Due date |
Description |
| #1 |
9/9 |
1.3c, 1.4, 1.5b, 1.9a, 1.14c, 1.15b,
1.18b,1.22 |
| #2 |
9/16 |
2.4e, 2.6, 2.11, 2.14, 2.18, 2.28 |
| #3 |
9/30 |
3.2d, 3.5c, 3.8d, 3.15d, 3.28 |
| #4 |
10/7 |
BCD-7-segment
dipslay |
| #5 |
10/13 |
Last homework before midterm 4.1, 4.27, 4.31, 4.32a |
| #6 |
11/4 |
5.4, 5.6, 5.8 (provide
the state equations too!), 5.10 (new duedate) |
| #7 |
11/11 |
4.49, 4.42 a, c, and d:
Submit Verilog files online. (new and different and
perhaps easier hwk#7) |
| #8 |
11/18 |
5.36: Provide gtkwave screen shot of the
simulation. Submit online: 1. xyz.v, 2. xyz.vvp, 3.
xyz.vcd, 4. screen shot of gtkwave output and 5. regular
output file captured using "script" commmand. All can be
zipped to one file hwk8.zip For online submission: get help from TAs/recitations |
| #9 |
12/2 |
5.18, 5.19, 5.41 |
| #10 |
12/6 |
5.50, 5.55, 5.56 |
| Exam (tentative) |
Date |
Material |
| Exam 1 |
10/16 8.00-9.50AM: 121 Cooke |
We will review |
| Final Exam |
12/11/2013 8.00-11.00,
121 Cooke |
Reviewing now |
Office hours (Extra help):
| Name |
Office hours |
Location |
Email |
| Bina |
MWF 10.10-11.10 |
345 Davis |
bina@buffalo.edu |
| Sanjiban |
W 3.00-5.00 |
302 Davis Lounge |
sanjiban@buffalo.edu |
| Jinghao Shi |
M 4.00-6.00, W 4.00-5.00 |
302 Davis Lounge |
jinghaos@buffalo.edu |
| Zhisheng Yan |
M 1100-12.00, TuTH 5.00-6.00 |
302 Davis Lounge |
zhisheng.yan@gmail.com |
| Victoria |
F 1.00-2.00 |
302 Davis Lounge |
vaminorc@buffalo.edu |
Also see the complete list of recitation, office hours etc. here.