Dr. Sridhar's Research Group Alumni
Ph.D.
Graduates:
Praveen Elakkumanan, Ph.D.
September 2006, Dissertation: “Overcoming the Circuit Design Challenges in Nanoscale SRAMs”; MS Thesis “Low
Leakage High Performance Static Random Access Memories”, Aug 2003– IBM Semiconductor Research and Development
Center,
Kris Schindler, Ph.D.February 2002, Thesis: "Energy Efficient Design Methodology for Combinational Logic Circuits" - University at Buffalo, CSE Department
Alfonso Martinez-Smith, Ph.D. 2000,
Dissertation: "Framework and Methodology for Object-Based Hybrid Visual
Processor Architecture Design" - Mutimedia
Research Lab, Motorola Corporation,
Wen-Jann Yang , Ph.D.,
SUNY at
Dipankar Talukdar, M.S. SUNY at
Sanu Mathew, M.S. September 1997, Thesis: "Efficient Clocking of Wave-Domino Pipelined Systems"; Ph.D. September 1999, Dissertation: "Data-driven Self-timed logic systems" - Intel Microprocessor research lab, Hillsboro, OR
Seokjin Kim,
M.S. 1993. Ph.D. 1997,
Dissertation: "Hierarchical Synchronization Scheme for Structured VLSI
Systems, AMD,
Yong-Chul
Shin, M.S. 1990, Thesis: "A General Purpose Parsing Processor for
LALR Class of Languages"; Ph.D. 1994,
Dissertation: "Non-Fully Configured Second-Order Neural Networks using
Multi-Dimensional Weights" - CTO, Cedar
Tech,
MS Graduates (Thesis)
Manjari Agarwal, M.S. August
2006, Thesis: “Charge-Sharing and Leakage Reduction in Domino CMOS Circuits”, -
Continuing Ph.D.
Karthik Ramakrishnan, M.S.
August 2006, Thesis: “Wireless Network Security using a Low cost Pseudo Random
Number Generator”, - Morgan Stanley, New York, NY
Kishan Prasad, M.S.
August 2005, Thesis: “Circuit Level Techniques for Reducing Radiation Induced
Soft Error Rate (SER) in Nanoscale Combinational
Circuits”
Aruna Balasubramanian,
M.S.
February 2005, “A Hybrid Security Solution for Mobile Ad Hoc Networks”,
Ghuru Kumaravelu,
M.S.
February 2005, “Virtual Cut ThroughSwitching for
Network on Chip Architectures”. Pactron/HJPC,
Vijaykumar Vankadara,
M.S.
September 2004, “Cache Hierarchy Design for Memory Intensive Applications”, Canto,
Camil Fayad, M.S. February 2004, Thesis: “
Roopa Raghunathan, M.S.
September 2003, Thesis: "Power Reduction through Effective Slack Timing
Utilization" – Magma Design Automation,
Ranjani Sridharan , M.S.
September 2003, Thesis: "Reconfigurable Opcodes
Instruction Set Architecture for Software Security" - Ph.D. at Texas A&M,
Srivathsan Krishnamohan, M.S.
September 2003, Thesis: "Orthoganal Instruction Set
Architecture for Network Capable Applicaiton
Processor" - Ph.D. student Michigan
State University,
Divya Chandrasekharan, M.S.
September 2003, Thesis: "Accurate Power Estimation at Register Transfer
Level with Leakage Consideration", - Mediatech,
Veena Pureswaran,
M. .S. 2001, Thesis:
"Reconfigurable DSP template for Multimedia processors” - IBM Corporation,
Anand Lakshmanan, M.S. May 2001, Thesis: "Noise tolerant dynamic circuit” - Intel Corporation
Subramanian Sankaran, M.S. February 2000, Thesis: "Crosstalk analysis and
clustered voltage scaling techniques in CMOS Designs" – Qualcomm,
Venkatesh Doraiswamy, M.S.
February 2000, Thesis: "Impact of Interconnects on Deep submicron
Wave-Pipeline designs" - Intel Corporation,
Shu Xia, M.S.- “Foveal Vision System Design
and characterization”, February 1999. Teradyne
Corporation,
Shahar Dor, M.S.
February 1998, Thesis: "On-line Delay-Fault Detection and Correction of
Reliable Wave-Pipelining" - Sun
Microsystems -
Jay Anderson,
M.S. August 1998, Thesis:
"A New Circuit State Retention Scheme for Multi-threshold Voltage CMOS
Circuits" -
Hemil B. Patel, M.S.
September 1998, Thesis: "Supply-Threshold Voltage Scaling for Speed-Power
Trade-Off" - LSI Logic
Daniel R. Pilhorn,
M.S. September 1998,
Thesis: "Issues in the Power Analysis of Digital Signal Processors" -
Lockheed Martin Federal Systems Division
Paul DeMarco, M.S. September 1998, Thesis: "Issues in the Design of a DSP FPGA Architecture" - Lockheed Martin Federal Systems Division
Guhan Krishnan, M.S. September 1998, Thesis: "Partial Binding
specifications for low power High Level Synthesis" – AMD,
Rajesh S. Parthasarathy, M.S.
August 1997, Thesis: "Design of Wave pipelined Arithmetic Units using
Double Pass Transistor Logic" - Intel
Corporation,
Mathew Greenberg, M.S.,
August 1997, Thesis: "A Hardware Implementation of a Two Dimensional
Discrete Cosine Transform" - Applied Signal
Technology,
Brian Bart, M.Eng.
1996. Project Title: "Foveal Vision sensor
prototype design" - Intel Corporation,
Folsom,
Brian McGee, M.S.
1995, Thesis: "Low Power Issues in Wave Pipelined Systems" -Sun Microsystems,
Enrique Fernadez Herrera, M.S. 1995,
"Dual Rail Static CMOS Architecture for Wave Pipelining" -
Universidad Centroamericana Jose Simeon Canas,
Ramkumar Krishnamurthy, M.S.
1994, Thesis: "Wave-pipelined CMOS Implementation of Morphological
Processors";
Xuguang Zhang, M.S.
1994 - PairGain Technologies
Inc.,
Frank K. Li, M.S. 1993, Thesis: "Practical Asynchronous Design Techniques and Analysis"
Sanjay Fotedar, M.S. 1993. Thesis: "Underline Detection and Removal System using Hough Transform" - NCR Corporation
Chandra S. Bharathi, M.S.
1993, Thesis: "Data Structures and Compression Techniques for a Large
Read-only Memory resident database", - Intersolv.
Parag Gokhale, M.S.
1992. Thesis: "System Controller and System Integration for the Real-time
Address Block Location System" - Accurate Corporation,
Douglas Hall, M.S. 1992. Thesis: "A Processor for
Symbolic and Numeric Applications.
Rajesh Dixit, M.S.
1992, Thesis: "Handwriting/Machine Print Discrimination and Character
Recognition in Address Block Location System" - Jones Inc,
Sudeep Narain, M.S. 1991, Thesis: "Design and Simulation of an Architectural Framework for an Intelligent Decision Support System".
Dirk Naumann, M.S.
1991, Thesis: "Design and Implementation of a Self-timed
Microprocessor"