Timing and control (The missing links)
What’s missing in the RTL description of DLX given above is the timing and control information:
For example: (Add R1,R2,R3)
Add.t0: IR <== Mem[PC], NPC <== PC + 4
Add.t1: A <== Regs[IR 6..10], B <== Regs[IR 11..15]
Add.t2: ALUoutput <== A op B;
Add.t3: do nothing (idling)
Add.t4: Regs[IR 16..20] <== ALUoutput