// Commands to simulate
//iverilog -o example1.vvp example1.v
//vvp example1.vvp
//To view the wave:
//gtkwave example1.vcd
// sequential Example 5_20 : the instantiation is inside
// the test bench

// item 1
module counter2 (output y, input x, input clock,input reset);

// item 2

   reg[1:0] state;  // 2 bits

// item 3
   parameter S0=2'b00, S1 = 2'b01, S2=2'b10, S3=2'b11;

//item 4 when and how do the state transitions happen?
   always@ (posedge clock, negedge reset)// event driven
     if (reset == 0) state <= S0;
     else case (state)
	    S0 : if(x==1) state <= S1; else state<= S0;
            S1 : if(x==1) state <= S2; else state<= S1;
            S2 : if(x == 1) state <= S3; else state<= S2;
            S3 : if(x == 1) state <= S0; else state<= S3;
	  endcase // case(state)
// item 5 : output

   assign    y = (state==S3);

endmodule // counter2

module counter2_tb;
   // stand alone
 // item 1 definitions
   reg x, clk, rst;

   wire y;


 // item 2 instantiate counter2
   counter2 C1(y, x, clk,rst);

 // item 3
   initial #200 $finish; // duration of your simulation testing

// item 4
   initial begin
      rst = 0;

      clk = 0;

      #5 rst = 1;

      repeat (16)
	#5  clk = ~clk;
   end


// item 5 for x
initial begin
 x = 1'b0;

 repeat(8)
 #10 x = ~x;
end

// item 6 for montioring, output text and waveform
initial begin
$monitor("x=   %d  y= %d",x,y);
$dumpfile("example1.vcd");
$dumpvars;
end

endmodule
//