00001 00007 /* Embedded XINU, Copyright (C) 2007. All rights reserved. */ 00008 00009 struct platform 00010 { 00011 char name[16]; 00012 void *maxaddr; 00013 ulong time_base_freq; 00014 uchar uart_dll; 00015 uchar uart_irqnum; 00016 }; 00017 00018 extern struct platform platform; 00019 00020 /* Max RAM addresses */ 00021 #define MAXADDR_DEFAULT 0x00800000 00022 #define MAXADDR_WRT54G 0x00800000 00023 #define MAXADDR_WRT54GL 0x01000000 00024 #define MAXADDR_WRT350N 0x02000000 00026 /* Time Base Frequency */ 00027 #define TIME_BASE_FREQ_WRT54G 120000000 00028 #define TIME_BASE_FREQ_WRT54GL 100000000 00029 #define TIME_BASE_FREQ_WRT350N 150000000 00030 #define TIME_BASE_FREQ_DEFAULT 100000000 00031 00032 /* UART DLL (Divisor Latch LS) */ 00033 #define UART_DLL_WRT54G 0x0E 00034 #define UART_DLL_WRT54GL 0x0B 00035 #define UART_DLL_WRT350N 0x29 00036 /* Baud divisor of 0x000B (11d) seems to work for the GL UART. */ 00037 /* Assuming x16 clock factor, that gives a base crystal frequency of */ 00038 /* about 20.275 MHz. */
1.5.5