module muxer;

   wire [3:0] i0, i1, i2, i3;


   wire [1:0] s;
   wire [3:0] y;


   
   mux4 m4 (i0, i1, i2, i3,s, y);
 
   mux4Test m4Test(y, i0, i1, i2, i3, s);
endmodule
   
   module mux4 (input [3:0] d0, d1,d2,d3, input [1:0] s, output [3:0] y);
  assign y = s[1]? (s[0]? d3:d2)
                 : (s[0]? d1:d0);
endmodule 

module mux4Test (input [3:0] y, output reg [3:0] d0, d1, d2, d3, output[1:0] s);
   
    reg [1:0] s;
       
    integer i;
    initial begin
       $monitor ("s: %d  y: ", s, y);
          d1 = 4;
          d2 = 5;
          d0 =3;
          d3 = 6;
       for (i=0; i<4; i=i+1)  begin s=i; #10 ; end $finish; end 
endmodule