Homework 2

1. Do a Power Simulation using SpectreS on a 2-Input NAND gate with the following width and lengths:

          P-transistor width = 10 lambda

          N-transistor width = 5 lambda

          P-transistor length = 2 lambda

          N-transistor length = 2 lambda.

        Increase the transistor sizes to

         P-transistor width = 18 lambda

         N-transistor width = 9 lambda.

        Repeat the power simulation for these values.

        Confirm that the power consumed increases with an increase in transistor sizes.

        Submit the plots of the instantaneous power and the values of the average power in each simulation.

Due as above: Monday 10/13/03 9:00pm Hardcopies should be turned in to the TAs. (Late submissions accepted at 10% penalty until Wednesday 10/15/03 4pm). Additionally, an electronic submission also should be made.

1. Also, due is a detailed project proposal that includes a full functional diagram, logic circuits and pin-outs. It should also include a description that gives the division of labor among the members, list of members and their email IDs and the setup where this chip will be used in the final application.

Due Wednesday 10/8/03 6:30 pm