March 15, 2001

The Test Design Automation Lab directed by Shambhu Upadhyaya, Associate Professor of Computer Science and Engineering has been expanded to include additional hardware and state-of-the-art chip design and test software. The lab has been commissioned today (3/15/01) and is ready for use in various classes and research. This semester, the lab will be used in CSE452/552: VLSI Testing with an enrollment of 40.

The expanded lab, located in Furnas 210 now consists of a brand new high-end RS6000 Powerserver, two additional RS6000 File Servers, a laserprinter and 14 Risc Desktop PowerPCs. The software includes IBM TestBench Release 2001 (a design for test synthesis and analysis tool), HiaSynth and BooleDozer (High level Synthesis tools), CircuitBench (circuit level design and simulator) and regular Unix compatible tools. With this expansion, we now have the basic infrastructure that is needed to develop and simulate large size testable chips in VLSI-related courses and research.

This lab was fully installed by IBM and will be maintained by IBM, adding significant value to the facility. This lab expansion was possible due to the IBM Faculty Partner Fellowship offered earlier to Prof. Upadhyaya.

Prof. Upadhyaya has also recently received a research grant ($32,165 for 12 months) from IBM to conduct research on the TestBench tool.

This new facility adds to other on-going partnership efforts in the CSE department such as the Center for Computational Research. An earlier version of this Test Design Automation Lab (which was in Trailer G) has been cited in the IBM webpage, that is publicly browsable. The URL is: http://www.chips.ibm.com/services/testbench/ (currently not operational) for anyone interested in knowing more about this lab.