CSE 493/593 Fall 2022
Cadence Tutorial

This tutorial assumes that you have started up Cadence and the CIW and Library Manager window are open. If they are not, please refer to the Cadence Setup page for this procedure.

Creating Circuit Schematic

Creating New Library:

All designs related to a project/homework are stored in a library. To create a new library from the Library Manager, click on File > New > Library. In the New Library window, type Lab1 as the name of the library and click OK:

In the Technology File for New Library window, select attach to existing technology library and click OK:

In the next window, select NCSU_TechLib_ami06 and click OK

Now the library Lab1 is created.

Creating new schematic design

In the Library Manager window, click on File > New > Cell View, and enter the following to create a schematic called Inverter and click OK

If the Upgrade License window appears, click Yes. The Virtuoso Schematic L tool appears, as shown below:

At this point, you have created a library called Lab1 and a cell inside it, called inverter. Now the design process can be started. For a full custom design, the process begins by creating a schematic. Then we simulate this design to verify the correctness of its functionality. Only after this is done, is the layout of the design performed. 

Now, we put down the design of the inverter in the Schematic Editor window. The Inverter consists of a NMOS and PMOS transistor with appropriately connected gate, drain and source terminals. The transistors and the input signal sources are instantiated and connected in the schematic editor. To instantiate a NMOS transistor :

Create Instance:

In the schematic window, click on Create->Instance (or type i). The "Add instance" dialogue box appears together with the "component Browser" dialog box. (In case the "Component Browser" does not appear, click on browse in the "Add Instance" dialog box to start it.)

In "Component Browser" window, Click on Library and choose NCSU_Analog_Parts. Click on N_Transistors and choose nmos4 as your NMOS device. To place the instance, activate the schematic window and click the left mouse button to put the instance at the place desired.

Note in Cadence schematic composers and layout editors, a command will not terminate unless the user cancels it or the user starts a new command. In this case, you can see another instance is ready to be placed right after you placed the first instance. To terminate the current operation (which is "add instance" in this case), press ESC key on the keyboard. In fact, you can always cancel the current operation in schematic or layout editors by pressing ESC key.

Edit Object Properties:

Now, we set the length and width of the NMOS transistor that is instantiated. To do this, select the object (NMOS transistor) by clicking on it and then go to "Edit > properties > Object..." (or by typing q). An object properties editing form will pop up. In this form, make the NMOS width 1.5u and length 600n, and click ok.

Repeat the Create Instance procedure for a PMOS transistor and set its width equal to 1.5u and length to 600n. The schematic should look similar to this:

Wiring up:

To connect the PMOS and NMOS devices or any electrical device, click on Create->Wire(narrow) in the schematic window (or type w). Click at the terminal where the wire starts and click at the terminal where the wire ends, a wire will be automatically added. If you are not satisfied with the automatic wiring, you can remove the wire and reroute it manually. This time, instead of clicking at the terminal where the wire ends directly, you can click the left mouse button whenever you want to change the wire direction.

If you want to stop the wire somewhere instead of connecting it to a terminal, double click your left mouse button and a dangling wire is created. In general dangling wire should be avoided, however, in some cases (like you want to label this wire or add a pin to this wire), a dangling wire makes sense.

In this case, connect the drain terminals of PMOS and NMOS, and the gate terminals of the PMOS and NMOS. Also, be sure to connect the bulk terminals of each transistor to its source. After all this wiring, the schematic should look similar to this :

Creating Supply Voltage Net (Vdd/gnd) and Input/Output pins:

To connect the source terminal of PMOS to Vdd, instantiate the object NCSU_Analog_parts>Supply_Nets>vdd and place on top of the PMOS in the schematic. Similarly instantiate NCSU_Analog_parts>Supply_Nets>gnd and place on bottom of the NMOS transistor. Connect the vdd terminal with the PMOS source terminal, and the gnd with NMOS source terminal. Next, create pins for input and output. Click on "Create->Pin..." (or type p) in the schematic window, the following dialogue box would appear:

Type in as the pin name. Note that the direction is listed as input. For an output pin, you would need to change this to output. Now  press Enter. Then in the schematic window, place the pin terminal on the wire that connects the gate terminals of the transistors. Similarly, create an out pin and set its direction as output. The out pin is placed on the wire connecting the drain terminals of the transistors. After this, the schematic should look similar to this:

After the design has been completed, click on "File->Check and Save" to check and save your designs, or use hotkey F8.
Check the CIW window to see if there are any errors or warnings in your design. If there are, then fix them and repeat Check & Save.

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Transient Simulation using ADE L

To simulate the current design, in the Virtuoso window, click on Launch > ADE L. If there is a dialog box about higher tiered license, click Yes. That brings up the Virtuoso Analog Design Environment window that looks similar to this:

The following points have to be taken care of before the design can be simulated –

·        Setup > Simulator/Directory/Host – specifies the simulator to use and where the simulation results will be stored. We will use spectre simulator and store the simulation results at <home directory>/vlsi/cadence location. Make sure the simulator/directory/host window is similar to this and click OK:





 

 

Once all inputs have been described, now we specify the global source Vdd. Click on the Global Sources radio button on the top, and setup the Vdd supply as DC voltage of 5v and click APPLY, as shown below. Then click OK.







 





·       f – fits waveform in current window display

·       z – zoom in

·       Z – zoom out

·       To zoom in to a rectangular area in the plot, left click mouse at the left bottom corner of the rectangular region you want to zoom in. Drag the mouse with left button clicked to the right top corner of the rectangular region and release mouse button

·       Markers – A and A. Press A on the keyboard, and marker A appears. Left click on a particular spot on a waveform, and the left hand bottom corner of the screen indicates the x and y values of the placed marker A. Similarly pressing A again initiates the marker A. After placing both markers, the bottom corner of the screen also mentions the difference (delta) between the x and y values of the two points. This may be useful in measuring delays and rise/fall times of signals

·       To view each of the waveforms individually in its own axis, click on the Strip Graph button, which is the third button after the printer icon below the File menu bar.

·       To produce a softcopy/hardcopy of a waveform window, click on File > Print. In the Print window, make sure the lp printer is selected and the Print to File is enabled. Click on Print button in the bottom right corner. In the Print to File dialog box, specify the name of the file you want the output to go to. For example if the output file should be inverterplot, then browse to the appropriate directory and type in the name as inverterplot.ps and press OK. That produced a postscript PS file. This can be directly printed to a printer using the unix lp command, or converted into a pdf file using the ps2pdf command in unix.

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Symbol Creation and Simulation

Symbols are useful when the schematic design is done hierarchically. At a higher of level of abstraction, we would like to use a symbol to replace the details of a cell. Because of this, a symbol of a cell design should define all the input pins and output pins of that cell explicitly.

Once you have completed the schematic design, you can create its symbol right from the schematic cell.

Click on Create > Cellview > From Cellview. Click OK on the Cellview From Cellview window and the next window.

 

This will pop-up another window that contains a default symbol picture, which is shown below. It has a red box that encloses the green colored inverter symbol. This red box defines the actual size a symbol will occupy, if you were to use this inverter symbol in another design. You can change the size of this box by clicking and dragging. It is good custom to exactly fit the symbol within the red box. The red square dots indicate the pin connections. [@InstanceName ] and [@PartName] are display variables, which you may delete or keep. The following picture shows the symbol.

 

If you don't like this rectangular symbol that is automatically created by the tool, you can create a symbol of you own by dragging the lines and input/output pins to their desired locations. An example is shown below, in which an inverter symbol is created which looks similar to the usual inverter gate symbol:

 

Once the symbol is created, it can be instantiated in any other cell design. For example, you may create a new schematic cell view (could be under the same library Lab1) to design a ring oscillator. A ring oscillator consists of a chain of inverters. You could instantiate the inverter symbol we just created. To do this - press hot key i or click on Create > Instance. In the component browser window, click on Lab1 > Inverter and place the required number of instances in the ring oscillator schematic.

After Checking and Saving the ring oscillator schematic, it can be simulated using the same procedure described above.

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Custom Layout using Layout XL

Now, we will go through custom layout using Layout L, by creating a layout for the inverter cell. To do this, in the Library Manager window, click on File > New > Cell View. Make sure the New File dialog box looks as below and click OK.

If the license window pops up, click YES. The Virtuoso Layout Suite L Editing window should open up along with the LSW window, as shown below:

 

The LSW window contains all the layers that would be used to draw the layout. To create the inverter layout, let us first instantiate the PMOS transistor. To do this, press hokey i or click on Create > Instance. In the create instance window, enter library name as NCSU_TechLib_ami06, cell as pmos, View as layout, Width as 1.5u, Length as 600n and press ENTER. Place the instance in the layout window. Similarly, instantiate a nmos transistor from the same library and place below the pmos transistor in the layout window. The layout should look similar to one shown below. Instead, if it appears as a red rectangle with pmos and nmos written on it, after instantiating, press ShiftF/ControlF to toggle views.

The red rectangle (poly layer) in the middle of each transistor is the gate of the transistor. The black filled rectangles on either side of the gate are vias and can be used interchangeably as source/drain terminals of the transistor. Now, we connect the gates of the pmos and nmos transistors using poly layer. Left click on the poly layer in the LSW window. Then switch back to the layout window and press rectangle hotkey r. The rectangle window appears. Switch back to the layout window, and left click at the left bottom corner of the rectangle you want to draw. Then left click at the top right corner of the rectangle you want to draw. Most hotkeys used in the schematic editor work in the layout editor too. After drawing a rectangle you might want to take a few minutes to familiarize yourself with manipulating the rectangle shape and size. Try using different hotkeys such as m for move, s for stretch and z/Z for zoom, f for Fit in Window, k to draw a scale. To cancel the current command, press ESC. At the end of this, the gates should be connected, as shown below:

Similarly, create a metal 1 wire (using rectangle) to connect the drains of the two transistors (connect the two vias, as shown below). Use more rectangles to draw out the wires. Next, create the in pin. This pin is going to be created on the poly layer. So click on poly in the LSW window. Then in the layout window, click on Create > Pin. Create the in pin by filling out the fields as shown below and press ENTER:

Place the pin on the poly wire connecting the two gates. To do this, click anywhere on the poly wire once. This will be the bottom left corner of the pin rectangle. Then click once again at the top right corner of the pin rectangle. Next, click next to pin where you want the pin name to appear. It is a good idea to make sure that the pin is placed at a location where there is only one layer underneath the pin, in this case the poly layer. This helps avoid confusion regarding which layer the pin is attached to. Similarly create the out pin as an output pin, the vdd! and gnd! pins as inputoutput pins, and place them on metal1, as shown below:

You may have noticed that the bulk terminal is missing in the above layout for the pmos and nmos transistors. At the layout level, one bulk connection is made for several adjacently placed transistors. In this case, we only have one pmos and nmos transistor. So we will still create the bulk connections for these transistors. To do this, instantiate ntap from NCSU_TechLib_AMI06 and place next to the pmos transistor. Instantiate a ptap from the same library and place next to the nmos transistor. Connect the terminals from the taps to the supply nets vdd and gnd, as shown below:

Now the layout is complete. The next step is to verify the layout satisfies the technology rules and then extract and simulate it. To verify the Design Rules Check (DRC) is passed, in the layout window, click on Verify > DRC. In the DRC window, select Join Nets with the Same Name and click OK. Then check the CIW window for errors.

If there are errors, they flash in white rectangles in the layout window. The find out what the error is, in the layout window, click on Verify > Markers > Explain. Then left click on any one of the flashing white rectangles. A window pops up explaining what the error at that location is. An example pop up window with a metal width error is shown below:

So use the ruler (hotkey k) to draw scale for your references near this metal strip and measure the width. Then resize your rectangle to satisfy the width requirement. Use this procedure to fix all errors. Then run DRC check again to ensure that error does not occur anymore. Once a particular marker’s error is fixed, you can delete that marker by clicking on Verify > Markers > Delete and clicking on that marker.  Repeat this process until there are no DRC errors. Then save the layout.

After this, the next step is to extract the electrical circuit netlist from this layout diagram. To do that, from the layout window, click on Verify > Extract. In the Extractor window, select Join Nets with Same Name, and click on Set Switches button. In the Set Switches window, click on the first option – Extract_parasitic_caps and press OK. Press OK in the extractor window. Look at the CIW window and make sure there are no errors.

If there are no errors, then the extracted view has been created. Goto the Library Manager window and open the extracted cell view for the inverter. It should look similar to the window shown below. If it doesn’t try toggling the view with ShiftF/ControlF.

Now the extracted layout is ready to be simulated. To simulate it, follow the same steps as specified in the Simulation section above.

To check if your design passes an LVS match, on your extracted view, click Verify then select LVS. Choose the right schematic and extracted views which you want to compare and hit Run. You should see a window pop up indicating if your netlists match or not.

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Layout Instantiations

Similar to creating symbols at the schematic level, your layouts can also be instantiated and repeatedly used several times while designing a hierarchical design. Let us go back to the inverter example. Create a new layout cell view for the inverter cell. Create an instance by clicking Create > Instance in the layout window. Then browse to the Lab1 library, inverter cell and select the layout. This can now be instantiated in your layout multiple times and used similar to the schematic symbols. The layout can be DRV verified, extracted and simulated using the steps described above.

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DC Analysis

Here, we will perform DC analysis of the inverter performance. To do it, we sweep the input DC voltage of the inverter and check the output DC voltage. We will first need to instantiate a voltage source for each input that is sweeped. In the inverter schematic window, instantiate NCSU_Analog_Parts > Voltage_Sources > vpulse. Connect the positive terminal to the input wire and the negative terminal to the ground, as shown below. Then, Check and Save.

To perform DC analysis simulation on the current design, in the Virtuoso window, click on Launch > ADE L. If there is a dialog box about higher tiered license, click Yes. That brings up the Virtuoso Analog Design Environment window that looks similar to this:

The following points have to be taken care of before the design can be simulated –

·        Setup > Simulator/Directory/Host – specifies the simulator to use and where the simulation results will be stored. We will use spectre simulator and store the simulation results at <home directory>/vlsi/cadence location. Make sure the simulator/directory/host window is similar to this and click OK:



 

·        Click on Setup > Stimuli. Click on the Global Sources radio button on the top, and setup the Vdd supply as DC voltage of 5v and click APPLY, as shown below. Then click OK.

 








 

 

 

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Waveform Calculator Tutorial

Waveform calculator can be used to perform may different measurements/transformations on the waveforms displayed in the waveform window. This includes – computing the average of a waveform (e.g. power) over the entire length of the simulation or in a given period of time, finding the propagation delay of between input and output signals, or addition/subtraction/multiplication/division of waveforms, etc.

Example: Let us compute the average power consumed in a circuit during time 0 to 2ns. To do this, make sure that before simulation you select the Outputs > Save All > power (all) option in the ADE window. Then simulate the circuit as usual, with simulation time more than 2ns.

To invoke the calculator tool, click on its icon in the waveform display window. The icon is located right below the “Marker” pull-down menu. The picture below shows the “:pwr” (this waveform is the instantaneous power consumed by the whole circuit) and “in” signals from an inverter simulation displayed in the waveform window.

The calculator window shown below appears. Make sure the “Wave” and “Clip” are selected.

Now switch back to the waveform window and left click the mouse once on the power waveform. Then switch back to the calculator window. It should look as shown below. The name of the waveform that you clicked on has appeared in the white box in the calculator.

Next, we will choose the operation to be performed on the waveform. To get the average power between 0 and 2ns, we first clip the waveform to the time interval of interest. To do this, click on the “clip” function in the list of functions towards the bottom of the calculator. That should result in a window similar to this –

Enter From = 0 and To = 2n in the fields. Then click on apply. Notice that the white box is updated now with the clip function applied. Now this expression needs to be evaluated/plotted. To do so, click on Tools > Plot in the calculator window. Switch back to the waveform window. Now there is the clipped waveform in a new sub window, similar to this –

 We now need to compute the average of this waveform. Switch back to the calculator window. If the clip function is still active in the bottom of the calculator, click on quit.  The white box in the calculator should now read something like “clip(getData(":pwr" ?resultsDir "./simulation/inverter/spectre/schematic" ?result "tran-tran") 0 2n )”. Select the average function from the list of functions in the calculator. Then click on Tools > Plot. This will print the average value in the white box in the calculator.

To select a different waveform and work on it in the calculator, simply go to the waveform window and click on the waveform of interest. The white box in the calculator will now be updated to that wave form.

Special Example: N-stage Ring Oscillator

1.    Schematic design: N=11

2.     

Option 1: Add ouput port (N=3)

Option 2: Add wire name

·        Add > Wire Name  to add the label.  Add label named TP and place it at the output of the last inverter.

 

·       

 

3. Simulation setup

Simulating this is largely the same as simulating a single inverter, with one major exception.  The output pin, out, also serves as the input for the gates at the first stage.  This means we need to assign an initial condition to that pin.

 

Having repeated the steps for an inverter, but omitting the input signal (as there is none),

 

Click Simulation -> Convergence Aids -> Initial Condition...

 

The schematic should come to the top again, with the Select Initial Condition Window.

 

Click on the 'out' pin, and the entire node should be highlighted.  Type in '0' in the Node Voltage Field.  Click 'OK' to save changes.

 

Selecting the proper transient stop time is important.  Here is the simulation output for a 1us stop time:

 

4. Output waveform and calculation

 

Now, let us calculate the oscillation period.  Click on calculator button as highlighted above.  In the Calculator window (shown below), select tran tab and vt under Selection choices.  Then click on delay, Virtuoso Schematic Editor window will pop up for you to select the waveform you want to probe: select TP and go back to the Calculator window.  It should look like this:

 

 

Both Signal1 and Signal2 fields should read VT(/TP).  Set Threshold Value 1 to VDD/2=2.5V  and Edge Number 1 to rising (falling is also OK).  Click on the >>> button to specify the second trigger point.  Specify parameters as indicated below:

 

 

Click on the >>> button to calculate the delay between the first and the second rising edge of signal TP.  Click OK, the following window will appear.

 

 

Click Eval button to evaluate the delay expression highlighted above.  The expression evaluates to 400ps as shown below.

 

 

This is the period of oscillation.  

 

In terms of gate delay, period T has a total of 11 low-to-high and 11 high-to-low transitions.

 

                        T = N∙(tpLH + tpHL),  where N is the number of stages (N=11)

                        Gate delay = tp = (tpLH+tpHL)/2

 

Therefore:          tp = T/2N

                        For N = 11:  tp = 400/22 = 18.1ps

 

 

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Acknowledgement: Some parts of this tutorial have been borrowed from the Cadence Tutorial website at the University of Texas at Austin.