@ARTICLE{xu:iet2019b,
author={C. {Guo} and J. {Xu} and W. {Xu} and H. {Zhang}},
journal={IET Radar, Sonar Navigation},
title={Reconfigurable missile-borne SAR imaging SoC design},
year={2019},
volume={13},
number={5},
pages={776-780},
keywords={CMOS integrated circuits;digital signal processing chips;field programmable gate arrays;integrated circuit design;missiles;radar imaging;synthetic aperture radar;system-on-chip;CMOS process;low power consumption;radar technology;integrated circuit manufacturing technology;SoC design;IP reuse;reconfigurable missile-borne SAR imaging SoC chip;configuring parameters;reconfigurable IP cores;synthetic aperture radar imaging system;real-time performance;size 0.13 mum},
doi={10.1049/iet-rsn.2018.5248},
ISSN={},
month={},}