Implementation of DLX’s ISA

• DLX instruction can be implemented in at most five cycles:

• Instruction fetch (IF):

  IR <== Mem[PC]
  
  NPC <== PC + 4

• Instruction decode (ID)

A <== Regs[IR 6..10]

B <== Regs[IR 11..15]

Imm <== IR 16..31 with sign

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