Implementation of DLX’s ISA

• Execution/Effective address (EX): Four alternatives:

• Mem. Reference :

ALUoutput <== A + Imm;

• Register-Register ALU inst:

ALUoutput <== A op B;

• Register-Immediate :

ALUoutput <== A op Imm;

• Branch:

ALUoutput <== NPC + Imm; Cond <== (A op 0)

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