Pipelining the DLX datapath
How do arrive at the above list of requirements? Examine what happens in each pipeline stage depending on the instruction type. Make a list of all the possibilities.
RTL statements of the events on every stage of the DLX pipeline is given in Fig.3.5.
To control this pipeline, we only need to determine how to set the control on the four multiplexers (mux)
- The first one inputs to PC. Lets call it MUX1.
- The next two the input to ALU: MUX2, MUX3
- The fourth one input to register file: MUX4