Pipelining the DLX datapath
1) Separate instruction and data caches eliminating a conflict that would arise between instruction fetch and data memory access. This is shown in the data path we studied earlier. This design avoids resource conflict.
2) We need to avoid register file access conflict: it is accessed once during ID and another time during WB stage.
3) Update PC every cycle. So mux from memory access stage is to be moved to IF stage.
4) All operations in one stage should complete within a clock cycle.
5) Values passed from one stage to the next must be placed in buffers/latches (I use buffers instead of registers to avoid confusion with regular registers).