Controlling the pipeline (contd.)
MUX2 and MUX3 are controlled by the type of instruction. MUX2 is set by whether the instruction is a branch or not. MUX3 is set by whether the instruction is Register-Register ALU operation or any other operation.
MUX4: is controlled by whether the instruction in the WB stage is a load or an ALU operation.
In addition there is one MUX which chooses the correct portion of the IR in the MEM/WB buffer to specify the register destination field.