Pipeline performance - Example1

• General: 40% ALU, 20% branch, 40% memory.

• Design1: Non- pipelined. 10ns clock cycles. ALU operations and branches take 4 cycles, memory operations take 5 cycles..In other words, ALU operations and branches take 4*10 = 40 ns time.

• Design 2: Pipelined. Clock skew and setup add 1 ns overhead to clock cycle.

• What is the speedup?

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