Desktop/xinu_mips-1.0.2.tar/xinu_mips-1.0.2/include/mips.h

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/* Embedded XINU, Copyright (C) 2007.  All rights reserved. */

#ifndef _MIPS_H
#define _MIPS_H

#define zero $0        
#define AT   $1        
#define v0   $2        
#define v1   $3
#define a0   $4        
#define a1   $5
#define a2   $6
#define a3   $7
#define t0   $8        
#define t1   $9
#define t2   $10
#define t3   $11
#define t4   $12
#define t5   $13
#define t6   $14
#define t7   $15
#define s0   $16       
#define s1   $17
#define s2   $18
#define s3   $19
#define s4   $20
#define s5   $21
#define s6   $22
#define s7   $23
#define t8   $24       
#define t9   $25
#define jp   $25       
#define k0   $26       
#define k1   $27
#define gp   $28       
#define sp   $29       
#define fp   $30       
#define s8   $30       
#define ra   $31       
#define CP0_INDEX    $0  
#define CP0_RANDOM   $1  
#define CP0_ENTRYLO0 $2  
#define CP0_ENTRYLO1 $3  
#define CP0_CONTEXT  $4  
#define CP0_PGMASK   $5  
#define CP0_WIRED    $6  
#define CP0_BADVADDR $8  
#define CP0_COUNT    $9  
#define CP0_ENTRYHI  $10 
#define CP0_COMPARE  $11 
#define CP0_STATUS   $12 
#define CP0_CAUSE    $13 
#define CP0_EPC      $14 
#define CP0_PRID     $15 
#define CP0_CONFIG   $16 
#define CP0_DIAG     $22 
#define CP0_TAGLO    $28 
#define CP0_TAGHI    $29
#define CP0_ERREPC   $30

#define PRID_REV   0x000000FF   
#define PRID_CPUID 0x0000FF00   
/* Processor revisions */
#define PRID_REV_WRT54G     0x29
#define PRID_REV_WRT54GL    0x08
#define PRID_REV_WRT350N    0x1A

#define CAUSE_EXC 0x0000007C   
#define CAUSE_SW0 0x00000100   
#define CAUSE_SW1 0x00000200
#define CAUSE_HW0 0x00000400   
#define CAUSE_HW1 0x00000800   
#define CAUSE_HW2 0x00001000
#define CAUSE_HW3 0x00002000
#define CAUSE_HW4 0x00004000
#define CAUSE_HW5 0x00008000   
#define STATUS_IE  0x00000001  
#define STATUS_EXL 0x00000002  
#define STATUS_ERL 0x00000004  
#define STATUS_SW0 CAUSE_SW0   
#define STATUS_SW1 CAUSE_SW1
#define STATUS_HW0 CAUSE_HW0   
#define STATUS_HW1 CAUSE_HW1   
#define STATUS_HW2 CAUSE_HW2
#define STATUS_HW3 CAUSE_HW3
#define STATUS_HW4 CAUSE_HW4
#define STATUS_HW5 CAUSE_HW5   
#define KUSEG_BASE 0x00000000  
#define KUSEG_SIZE 0x80000000  
#define KSEG0_BASE 0x80000000  
#define KSEG0_SIZE 0x20000000  
#define KSEG1_BASE 0xA0000000  
#define KSEG1_SIZE 0x20000000  
#define KSEG2_BASE 0xC0000000  
#define KSEG2_SIZE 0x40000000  
#define CONTEXT 64             
#define CONTEXT_WORDS (CONTEXT / sizeof(long))

#define RA_CON  (CONTEXT - 8)  
#define S0_CON  52             
#define S1_CON  48
#define S2_CON  44
#define S3_CON  40
#define S4_CON  36
#define S5_CON  32
#define S6_CON  28
#define S7_CON  24
#define GP_CON  20             
#define FP_CON  16             
#define CONFIG1_IS    22       
#define CONFIG1_IL    19
#define CONFIG1_IA    16
#define CONFIG1_DS    13       
#define CONFIG1_DL    10
#define CONFIG1_DA     7
#define CONFIG1_MASK   7       
#define INDEX_STORE_TAG_I  0x8  
#define FILL_I_CACHE       0x14 
#define INDEX_STORE_TAG_D  0x9  
#endif  /* _MIPS_H */

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