Desktop/xinu_mips-1.0.2.tar/xinu_mips-1.0.2/include/mips.h File Reference

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Defines
#define	zero   $0
#define	AT   $1
#define	v0   $2
#define	v1   $3
#define	a0   $4
#define	a1   $5
#define	a2   $6
#define	a3   $7
#define	t0   $8
#define	t1   $9
#define	t2   $10
#define	t3   $11
#define	t4   $12
#define	t5   $13
#define	t6   $14
#define	t7   $15
#define	s0   $16
#define	s1   $17
#define	s2   $18
#define	s3   $19
#define	s4   $20
#define	s5   $21
#define	s6   $22
#define	s7   $23
#define	t8   $24
#define	t9   $25
#define	jp   $25
#define	k0   $26
#define	k1   $27
#define	gp   $28
#define	sp   $29
#define	fp   $30
#define	s8   $30
#define	ra   $31
#define	CP0_INDEX   $0
#define	CP0_RANDOM   $1
#define	CP0_ENTRYLO0   $2
#define	CP0_ENTRYLO1   $3
#define	CP0_CONTEXT   $4
#define	CP0_PGMASK   $5
#define	CP0_WIRED   $6
#define	CP0_BADVADDR   $8
#define	CP0_COUNT   $9
#define	CP0_ENTRYHI   $10
#define	CP0_COMPARE   $11
#define	CP0_STATUS   $12
#define	CP0_CAUSE   $13
#define	CP0_EPC   $14
#define	CP0_PRID   $15
#define	CP0_CONFIG   $16
#define	CP0_DIAG   $22
#define	CP0_TAGLO   $28
#define	CP0_TAGHI   $29
#define	CP0_ERREPC   $30
#define	PRID_REV   0x000000FF
#define	PRID_CPUID   0x0000FF00
#define	PRID_REV_WRT54G   0x29
#define	PRID_REV_WRT54GL   0x08
#define	PRID_REV_WRT350N   0x1A
#define	CAUSE_EXC   0x0000007C
#define	CAUSE_SW0   0x00000100
#define	CAUSE_SW1   0x00000200
#define	CAUSE_HW0   0x00000400
#define	CAUSE_HW1   0x00000800
#define	CAUSE_HW2   0x00001000
#define	CAUSE_HW3   0x00002000
#define	CAUSE_HW4   0x00004000
#define	CAUSE_HW5   0x00008000
#define	STATUS_IE   0x00000001
#define	STATUS_EXL   0x00000002
#define	STATUS_ERL   0x00000004
#define	STATUS_SW0   CAUSE_SW0
#define	STATUS_SW1   CAUSE_SW1
#define	STATUS_HW0   CAUSE_HW0
#define	STATUS_HW1   CAUSE_HW1
#define	STATUS_HW2   CAUSE_HW2
#define	STATUS_HW3   CAUSE_HW3
#define	STATUS_HW4   CAUSE_HW4
#define	STATUS_HW5   CAUSE_HW5
#define	KUSEG_BASE   0x00000000
#define	KUSEG_SIZE   0x80000000
#define	KSEG0_BASE   0x80000000
#define	KSEG0_SIZE   0x20000000
#define	KSEG1_BASE   0xA0000000
#define	KSEG1_SIZE   0x20000000
#define	KSEG2_BASE   0xC0000000
#define	KSEG2_SIZE   0x40000000
#define	CONTEXT   64
#define	CONTEXT_WORDS   (CONTEXT / sizeof(long))
#define	RA_CON   (CONTEXT - 8)
#define	S0_CON   52
#define	S1_CON   48
#define	S2_CON   44
#define	S3_CON   40
#define	S4_CON   36
#define	S5_CON   32
#define	S6_CON   28
#define	S7_CON   24
#define	GP_CON   20
#define	FP_CON   16
#define	CONFIG1_IS   22
#define	CONFIG1_IL   19
#define	CONFIG1_IA   16
#define	CONFIG1_DS   13
#define	CONFIG1_DL   10
#define	CONFIG1_DA   7
#define	CONFIG1_MASK   7
#define	INDEX_STORE_TAG_I   0x8
#define	FILL_I_CACHE   0x14
#define	INDEX_STORE_TAG_D   0x9

---

Detailed Description

Define human readable registers, coprocessor 0 registers, cause and status register masks, memory segment addresses, context record offsets, and cache functions and register offsets.

Id

mips.h 235 2007-07-12 22:52:09Z agember

Definition in file mips.h.

---

Define Documentation

#define a0   $4

argument 0 to 3

Definition at line 23 of file mips.h.

#define a1   $5

Definition at line 24 of file mips.h.

#define a2   $6

Definition at line 25 of file mips.h.

#define a3   $7

Definition at line 26 of file mips.h.

#define AT   $1

asm temp - uppercase because of ".set at"

Definition at line 20 of file mips.h.

#define CAUSE_EXC   0x0000007C

Cause register interrupt masks Exception Code

Definition at line 96 of file mips.h.

#define CAUSE_HW0   0x00000400

Hardware interrupt

Definition at line 99 of file mips.h.

#define CAUSE_HW1   0x00000800

UART interrupt

Definition at line 100 of file mips.h.

#define CAUSE_HW2   0x00001000

Definition at line 101 of file mips.h.

#define CAUSE_HW3   0x00002000

Definition at line 102 of file mips.h.

#define CAUSE_HW4   0x00004000

Definition at line 103 of file mips.h.

#define CAUSE_HW5   0x00008000

Timer interrupt

Definition at line 104 of file mips.h.

#define CAUSE_SW0   0x00000100

Software interrupt

Definition at line 97 of file mips.h.

#define CAUSE_SW1   0x00000200

Definition at line 98 of file mips.h.

#define CONFIG1_DA   7

Definition at line 160 of file mips.h.

#define CONFIG1_DL   10

Definition at line 159 of file mips.h.

#define CONFIG1_DS   13

data cache

Definition at line 158 of file mips.h.

#define CONFIG1_IA   16

Definition at line 157 of file mips.h.

#define CONFIG1_IL   19

Definition at line 156 of file mips.h.

#define CONFIG1_IS   22

Cache register locations within the Config1 register instruction cache

Definition at line 155 of file mips.h.

#define CONFIG1_MASK   7

value mask

Definition at line 161 of file mips.h.

#define CONTEXT   64

Context record offsets context record size in bytes context record size in words

Definition at line 136 of file mips.h.

#define CONTEXT_WORDS   (CONTEXT / sizeof(long))

Definition at line 138 of file mips.h.

Referenced by create().

#define CP0_BADVADDR   $8

Bad address generated by TLB exceptions

Definition at line 64 of file mips.h.

#define CP0_CAUSE   $13

Identifies cause of interrupt/exception

Definition at line 69 of file mips.h.

#define CP0_COMPARE   $11

interrupt when CP0_COUNT == CP0_COMPARE

Definition at line 67 of file mips.h.

#define CP0_CONFIG   $16

configuration register (select 0, 1)

Definition at line 72 of file mips.h.

#define CP0_CONTEXT   $4

Hold PTE base and VPN on TLB exception

Definition at line 61 of file mips.h.

#define CP0_COUNT   $9

Timer counter

Definition at line 65 of file mips.h.

#define CP0_DIAG   $22

implementation dependent (diagnostic?)

Definition at line 73 of file mips.h.

#define CP0_ENTRYHI   $10

Hi half of TLB (VPN+ASID)

Definition at line 66 of file mips.h.

#define CP0_ENTRYLO0   $2

Even page TLB entry

Definition at line 59 of file mips.h.

#define CP0_ENTRYLO1   $3

Odd page TLB entry

Definition at line 60 of file mips.h.

#define CP0_EPC   $14

Return address after exception handling

Definition at line 70 of file mips.h.

#define CP0_ERREPC   $30

Definition at line 76 of file mips.h.

#define CP0_INDEX   $0

Coprocessor 0 registers Index pointer into TLB

Definition at line 57 of file mips.h.

#define CP0_PGMASK   $5

Mask for virtual address on TLB matching

Definition at line 62 of file mips.h.

#define CP0_PRID   $15

processor identification

Definition at line 71 of file mips.h.

#define CP0_RANDOM   $1

Random pointer into TLB

Definition at line 58 of file mips.h.

#define CP0_STATUS   $12

Various run time processor information

Definition at line 68 of file mips.h.

#define CP0_TAGHI   $29

Definition at line 75 of file mips.h.

#define CP0_TAGLO   $28

Definition at line 74 of file mips.h.

#define CP0_WIRED   $6

Boundary between random and wired entries

Definition at line 63 of file mips.h.

#define FILL_I_CACHE   0x14

fill instruction cache

Definition at line 167 of file mips.h.

#define fp   $30

frame pointer

Definition at line 50 of file mips.h.

#define FP_CON   16

frame pointer

Definition at line 150 of file mips.h.

#define gp   $28

global pointer

Definition at line 48 of file mips.h.

#define GP_CON   20

global pointer

Definition at line 149 of file mips.h.

#define INDEX_STORE_TAG_D   0x9

invalidate data cache tag

Definition at line 168 of file mips.h.

#define INDEX_STORE_TAG_I   0x8

Cache functions invalidate instruction cache tag

Definition at line 166 of file mips.h.

#define jp   $25

PIC jump register

Definition at line 45 of file mips.h.

#define k0   $26

kernel scratch

Definition at line 46 of file mips.h.

#define k1   $27

Definition at line 47 of file mips.h.

#define KSEG0_BASE   0x80000000

kernel unmapped, cached base

Definition at line 126 of file mips.h.

Referenced by nulluser(), platforminit(), and xsh_memstat().

#define KSEG0_SIZE   0x20000000

kernel unmapped, cahced (512 MB)

Definition at line 127 of file mips.h.

#define KSEG1_BASE   0xA0000000

kernel unmapped, uncached base

Definition at line 128 of file mips.h.

#define KSEG1_SIZE   0x20000000

kernel unmapped, uncached (512 MB)

Definition at line 129 of file mips.h.

#define KSEG2_BASE   0xC0000000

kernel mapped base

Definition at line 130 of file mips.h.

#define KSEG2_SIZE   0x40000000

kernel mapped (1 GB)

Definition at line 131 of file mips.h.

#define KUSEG_BASE   0x00000000

Define kernel memory segments for MIPS32 processors userspace mapped base

Definition at line 124 of file mips.h.

#define KUSEG_SIZE   0x80000000

userspace mapped (2 GB)

Definition at line 125 of file mips.h.

#define PRID_CPUID   0x0000FF00

CPU ID

Definition at line 82 of file mips.h.

#define PRID_REV   0x000000FF

Processor ID masks Revision

Definition at line 81 of file mips.h.

Referenced by platforminit().

#define PRID_REV_WRT350N   0x1A

Definition at line 91 of file mips.h.

Referenced by platforminit().

#define PRID_REV_WRT54G   0x29

Platform specific values and macros

Definition at line 89 of file mips.h.

Referenced by platforminit().

#define PRID_REV_WRT54GL   0x08

Definition at line 90 of file mips.h.

Referenced by platforminit().

#define ra   $31

return address

Definition at line 52 of file mips.h.

#define RA_CON   (CONTEXT - 8)

return address

Definition at line 140 of file mips.h.

#define s0   $16

callee saved 0 to 7

Definition at line 35 of file mips.h.

#define S0_CON   52

callee saved registers

Definition at line 141 of file mips.h.

#define s1   $17

Definition at line 36 of file mips.h.

#define S1_CON   48

Definition at line 142 of file mips.h.

#define s2   $18

Definition at line 37 of file mips.h.

#define S2_CON   44

Definition at line 143 of file mips.h.

#define s3   $19

Definition at line 38 of file mips.h.

#define S3_CON   40

Definition at line 144 of file mips.h.

#define s4   $20

Definition at line 39 of file mips.h.

#define S4_CON   36

Definition at line 145 of file mips.h.

#define s5   $21

Definition at line 40 of file mips.h.

#define S5_CON   32

Definition at line 146 of file mips.h.

#define s6   $22

Definition at line 41 of file mips.h.

#define S6_CON   28

Definition at line 147 of file mips.h.

#define s7   $23

Definition at line 42 of file mips.h.

#define S7_CON   24

Definition at line 148 of file mips.h.

#define s8   $30

same like fp!

Definition at line 51 of file mips.h.

#define sp   $29

stack pointer

Definition at line 49 of file mips.h.

#define STATUS_ERL   0x00000004

Error Level

Definition at line 111 of file mips.h.

#define STATUS_EXL   0x00000002

Exception Level

Definition at line 110 of file mips.h.

#define STATUS_HW0   CAUSE_HW0

Hardware interrupt enable

Definition at line 114 of file mips.h.

#define STATUS_HW1   CAUSE_HW1

UART interrupt enable

Definition at line 115 of file mips.h.

#define STATUS_HW2   CAUSE_HW2

Definition at line 116 of file mips.h.

#define STATUS_HW3   CAUSE_HW3

Definition at line 117 of file mips.h.

#define STATUS_HW4   CAUSE_HW4

Definition at line 118 of file mips.h.

#define STATUS_HW5   CAUSE_HW5

Timer interrupt enable

Definition at line 119 of file mips.h.

#define STATUS_IE   0x00000001

Status register masks Global interrupt enable

Definition at line 109 of file mips.h.

#define STATUS_SW0   CAUSE_SW0

Software interrupt enable

Definition at line 112 of file mips.h.

#define STATUS_SW1   CAUSE_SW1

Definition at line 113 of file mips.h.

#define t0   $8

caller saved 0 to 7

Definition at line 27 of file mips.h.

#define t1   $9

Definition at line 28 of file mips.h.

#define t2   $10

Definition at line 29 of file mips.h.

#define t3   $11

Definition at line 30 of file mips.h.

#define t4   $12

Definition at line 31 of file mips.h.

Referenced by test_schedule().

#define t5   $13

Definition at line 32 of file mips.h.

Referenced by t5(), and test_recursion().

#define t6   $14

Definition at line 33 of file mips.h.

#define t7   $15

Definition at line 34 of file mips.h.

#define t8   $24

caller saved 8 and 9

Definition at line 43 of file mips.h.

#define t9   $25

Definition at line 44 of file mips.h.

#define v0   $2

return value

Definition at line 21 of file mips.h.

#define v1   $3

Definition at line 22 of file mips.h.

#define zero   $0

Human readable register names wired zero

Definition at line 19 of file mips.h.