Lab 6: Verilog Description and Simulation of Combinational and Sequential Circuits

November 10 by Bina

Learning outcomes:

The learning outcomes are divided into two aspects (i) the concepts (ii) the process.

Concepts: On completion of this lab students will be able to:
LO1. Write a Verilog description of a combinational circuit, a test bench for it and simulate it.
LO2. Write a Verilog description of a sequential circuit, a test bench for it and simulate it.

Process: On completion of this lab students will be able to:
LO3. Login into CSE timberlake Linux server and work with command line interface (CLI)
LO4. Use an editor such as vim or nano to enter, edit and save a Verilog description
LO5. Use iverilog (Icarus Verilog) suite of commands to process the Verilog file
LO6. Create a script file capturing the development process
LO7. Transfer files from CSE server to your own local machines
LO8. Submit the lab work file to ublearns for grading.

Problem Statement:


Problem 1: Design a structural Verilog description and a test bench for the combinational circuit given below and store it in a file (lab6Comb.v). Compile it, debug it and simulate the execution, debug any issues and record the output of the correct simulation.
Circuit Diagram for Problem 1.

Problem 2:Design a behavioral description for the sequential circuit description given below as the finite state machine and store it in a file (lab6Seq.v). Design the suitable test bench for it and include it the same file. Compile, debug it and record the output of the correct simulation.
Finite state machine for Problem 2.

What to do?

  1. (LO1, LO2) Read the problems and understand the requirements.
  2. (L01) Prepare the Verilog solution for the Problem 1 on paper. Description of the circuit and the test bench for it.
  3. (L03) Connect to the CSE server timberlake.cse.buffalo.edu using the steps given in this document. If you Apple Macs or Linux machines you can directly connect using ssh.timberlake.cse.buffalo.edu
  4. (L04) Open an editor for entering the Verilog description you prepared in step 2. For the editor you can use vim. Commands for vim are availablevim editor commands sheet here.
  5. (L04) First item you want to enter in the file is a "name box" that provides information about the contents of the file you are creating.
    6. 
/******************************************************************************/
/* Program Name: lab6Comb.v                                                   */
/* Description: Verilog description and test bench for a combinational circuit*/
/* Author: Your name                                                          */
/* Person number(s):                                                          */
/* Date of completion:                                                        */
/* To Compile: iverilog lab6Comb.v -o lab6Comb.vvp                            */
/* To test/execute: vvp lab6Comb.vvp                                          */
/******************************************************************************/
    By entering your name in this box you agree to abide by the Academic Integrity rules of the course and that you authored the code entered below this box.
  6. (L05) Now enter the Verilog module for the Problem 1. Compile and make sure it is syntatically correct.
  7. (L05) Add the Test bench module for the Problem 1 to the same file. Complie and debug all the syntax errors.
  8. (L05) Execute the compiled vvp file and debug any execution errors. After it runs without any errors, study the output and make sure that it is as expected, and that proves that your circuit description is correct.
  9. (L05) Now repeat the steps for the Problem 2. Let the file name be lab6Seq.v
  10. Next step is to capture all your work into a single file.
  11. (L06) At the command prompt type script yourlastNameL6. This will start recording all the commands and outputs after this command into the file specified. And type all the comamnds listed below.
    12. 
ls -l
echo your name
echo Problem 1
cat lab6Comb.v
iverilog lab6Comb.v -o lab6Comb.vvp
vvp lab6Comb.vvp
echo Problem 2
cat lab6Seq.v
iverilog lab6Seq.v -o lab6Seq.vvp
vvp lab6Seq.vvp
ls -l
cntrl-d
  12. Now the file yourlastNameL6 is ready for submission.If you make a mistake in typing the above commands do not worry. Just retype it on a new line. Thats all.
  13. (L07) Transfer the file to your local machine using Filezilla or such tool.
  14. (L08) Next step is to submit the single file into the ublearns Lab6 link.
  15. Congratulations! Your have completed your first Verilog project and learned working with the CSE Linux server.

Grading

Problem 1: 50%
Problem 2: 50%