Digital logic circuits enable many of the modern devices, instruments, computers, drones, cell phones and automobiles. In this course we will learn the foundaton of digital logic and how to apply these to analyze and synthesize digital systems.
The objectives of this course are to introduce the fundamentals of digital logic design. On completion of this course, a student in this course should: (i) understand the fundamentals of Boolean algebra and apply it to design Boolean expressions for real world problems (ii) understand logic gates and their operation (iii) be able to design minimized combinational logic circuits using Karnaugh-map simplification (iv) understand how signed integers are represented in a digital system (v) understand how addition and subtraction are performed in hardware (vi) understand the integrated circuit chips used in digital system design, such as decoders, encoders, multiplexors, latches, flip-flops, and registers (vii) be able to design a combinational logic system using the above mentioned ICs and logic gates (viii) be able to design a finite state machine, allowing a real world problem to be solved using hardware (ix) design sequential circuits such as counters, and (x) describe and test digital circuits using a hardware description language.| Website | http://www.cse.buffalo.edu/~bina/cse241/spring2017 |
| Instructor | Bina Ramamurthy (bina@buffalo.edu) |
| Office Hours | MWF: 11.00-11.50AM |
| Office Location | 345 Davis |
| Lecture Time | MWF: 10.00-10.50AM |
| Lecture location | NSC 201 |
| Learning Outcome | Assessment Activity |
|---|---|
| Understand and apply Boolean Algebra | Hwk1, Exam1 |
| Understand logic gates and their operation | Hwk2, lab1, Exam1 |
| Understand K-map simplification of logic expression | Hwk3, lab2, Exam1 |
| Understand signed and unsigned integer represnetation and arithmetic | Hwk3, Exam1 |
| MSI circuits decoders, multiplexers and designing combinational circuits | Hwk4, lab3, Exam2 |
| Flip-flops, and sequential circuit synthesis | Hwk5, lab4, Exam2 |
| Verilog hardware description, synthesis and simulation | Hwk6, lab5, Exam2 |
| Reg# | Rec# | Day | Time | Location |
|---|---|---|---|---|
| 15383 | R1 | W | 8:00 AM - 8:50 AM | Hoch 139 |
| 15315 | R2 | T | 3:00 PM - 3:50 PM | Cooke 127A |
| 15323 | R3 | W | 3:00 PM - 3:50 PM | Hoch 139 |
| 15327 | R4 | R | 9:00 AM - 9:50 AM | Cooke 127A |
| 15328 | R5 | F | 3:00 PM - 3:50 PM | Cooke 127A |
| 22290 | R6 | M | 8:00 AM - 8:50 AM | Norton 214 |
Grades will consist of the following components:
Attendance 5%
Homework (5/6) and Labs (3/4)+ Lab5 40%
Exams (2) 20% + 35%
Letter grade guideline will be as follows:
95-100: A, 90-94.99: A-, 85-89.99: B+, 80-84.99: B, 75-79.99: B-, 70-74.99: C+, 65-69.99: C, 60-64.99: C-, 55-59.99: D+, 50-54.99: D, <50: F.
The instructor reserves the right to alter component weighting or provide a curve on an assignment as warranted.
COMPONENT PASS POLICY:
IN ORDER TO PASS THIS COURSE,
YOU MUST HAVE PASSING WEIGHTED COMPONENT AVERAGES
(WEIGHTED COMPONENT AVERAGES MUST BE GREATER THAN 49.99%).
THERE WILL BE THREE COMPONENTS THIS SEMESTER.
COMPONENT 1 IS THE EXAM COMPONENT CONSISTING OF THE TWO EXAMS.
COMPONENT 2 IS THE HOMEWORK COMPONENT.
COMPONENT 3 IS THE LAB COMPONENT.
There will be two exams one of which will be administered and graded before the resign date. Exam material will cover all lecture and reading assignments before the exam, as well as concepts from the homework assignments. Exams are closed book, closed notes, and closed neighbor. No makeup exam will be given. Exam 1 is during midterm exam week and final exam (exam 2) is during the final exam week.
Homework and Labs 40%There will be several homework assignments during the semester. These will be assigned during the lectures and will be turned in a week after it is assigned. You will submit the completed homework during lecture before the lecture begins. No late home works will be accepted. For overall grade computation we will include best 5 grades out of the 6 homework assigned. For the labs will include best grades from 3 best out of first 4 labs, and mandatory lab5. . We will provide more details under the Lab tab later.
Attendance Policy 5%You are responsible for the contents of all lectures and recitations (your assigned section). If you know that you are going to miss a lecture or a recitation, have a reliable friend take notes for you. Of course, there is no excuse for missing due dates or exam days. We do, however, reserve the right to take attendance in both lecture and recitation.
Grading PolicyAll assignments will be graded and returned in a timely manner. When an assignment is returned, you will have a period of one week to contest any portion of the grade. The TA who graded your assignment will be the first person to resolve a grading conflict. If the conflict cannot be resolved, the instructor will mediate the dispute. The judgment of the instructor will be final in all such cases. When contesting a grade, you must be able to demonstrate how your particular solution is correct. Also, when contesting a grade, the instructor or TA reserves the right to re-evaluate the entire lab or exam, not just the portion in dispute.
Digital Design: With an Introduction to the Verilog HDL by M. Morris Mano and Michael D. Ciletti, Prentice Hall; 5 edition (January 12, 2012), ISBN-13: 978-0132774208 Attendance Policy: You are responsible for the contents of all lectures and recitations (your assigned section). If you know that you are going to miss a lecture or a recitation, have a reliable friend take notes for you. Of course, there is no excuse for missing due dates or exam days. We do, however, reserve the right to take attendance in both lecture and recitation. We may use this information to determine how to resolve borderline grades at the end of the course, especially if we see a lack of attendance and participation during lecture sessions. During lectures, we will be covering material from the textbook. We will also work out several of the problems from the text. Lecture will also consist of the exploration of several real world problems not covered in the book. You will be given a reading assignment at the end of each lecture for the next class.
Incomplete Policy: We only grant incompletes in this course under the direst of circumstances. By definition, an incomplete is warranted if the student is capable of completing the course satisfactorily, but some traumatic event has interfered with their capability to finish within the timeframe of the semester. Incompletes are not designed as stalling tactic to defer a poor performance in a class.
Academic Integrity Policy: UB's definition of Academic Integrity in part is, "Students are responsible for the honest completion and representation of their work". It is required as part of this course that you read and understand the departmental academic integrity policy located at the following URL:
http://www.cse.buffalo.edu/undergrad/policy_academic.php
There is a very fine line separating conversation pertaining to concepts and academic dishonesty. You are allowed to converse about general concepts, but in no way are you allowed to share code or have one person do the work for others. You must abide by the UB and Departmental Academic Integrity policy at all times. NOTE: Remember that items taken from the Internet are also covered by the academic integrity policy! If you are unsure if a particular action violates the academic integrity policy, assume that it does until you receive clarification from the instructor. We reserve the right to check or question any portion of any work submitted at any time during the semester or afterwards. If you are caught violating the academic integrity policy, you will minimally receive a ZERO in the course.
Exams Policy: There will be a midterm (Exam 1) that will be administered and graded before the resign date. Midterm material will cover all lecture and reading assignments before the exam, as well as concepts from the project assignments. Midterms are closed book, closed notes, and closed neighbor. The second exam (Exam 2) will be covering all lecture material after exam1 and all the projects. We do not give make up exams for any reason. If you miss an exam, you will receive a zero for that portion of the grade. Second exam will be on the last day of classes.