00001 00007 /* Embedded XINU, Copyright (C) 2007. All rights reserved. */ 00008 00009 #include <uart.h> 00010 #include <kernel.h> 00011 #include <platform.h> 00012 #include <interrupt.h> 00013 #include <device.h> 00014 #include <mips.h> 00015 #include <stdlib.h> 00016 00017 struct uart uarttab[NUART]; 00018 extern void uartIntr(void); 00019 extern long cpuid; 00020 00025 devcall uartInit(device *pdev) 00026 { 00027 struct uart *puart; 00028 struct uart_csreg *pucsr; 00029 00030 /* Initialize structure pointers */ 00031 puart = uarttab + pdev->minor; 00032 bzero((void *)puart, sizeof(struct uart)); 00033 pdev->controlblk = (void *)puart; 00034 puart->dev = pdev; 00035 puart->csr = (struct uart_csreg *)pdev->csr; 00036 pucsr = puart->csr; 00037 00038 /* Initialize statistical counts */ 00039 puart->cout = 0; 00040 puart->cin = 0; 00041 puart->lserr= 0; 00042 puart->ovrrn= 0; 00043 puart->iirq = 0; 00044 puart->oirq = 0; 00045 00046 /* Initialize input buffer */ 00047 puart->isema = newsem(0); 00048 puart->iflags = 0; 00049 puart->istart = 0; 00050 puart->icount = 0; 00051 00052 /* Initialize output buffer */ 00053 puart->osema = newsem(UART_OBLEN); 00054 puart->oflags = 0; 00055 puart->ostart = 0; 00056 puart->ocount = 0; 00057 puart->oidle = 1; 00058 00059 /* Set baud rate */ 00060 pucsr->lcr = UART_LCR_DLAB; /* Set Divisor Latch Access Bit */ 00061 pucsr->dll = platform.uart_dll; /* Set Divisor Latch Low Bytel */ 00062 pucsr->dlm = 0x00; /* Set Divisor Latch High Byte */ 00063 00064 pucsr->lcr = UART_LCR_8N1; /* 8 bit, No Parity, 1 Stop */ 00065 pucsr->fcr = 0x00; /* Disable FIFO for now */ 00066 pucsr->mcr = UART_MCR_OUT2; /* Turn on user-defined OUT2. */ 00067 /* OUT2 is used to control the board's interrupt tri-state */ 00068 /* buffer. It should be set high to generate interrupt properly. */ 00069 00070 /* Enable interrupts */ 00071 pucsr->ier = UART_IER_ERBFI | UART_IER_ETBEI | UART_IER_ELSI; 00072 00073 /* Enable UART hardware FIFOs, clear contents and set interrupt trigger level */ 00074 puart->csr->fcr = UART_FCR_EFIFO | UART_FCR_RRESET | UART_FCR_TRESET | UART_FCR_TRIG2; 00075 00076 /* Enable processor handling of UART interrupt requests */ 00077 interruptVector[IRQ_UART] = pdev->inintr; 00078 enable_irq(pdev->inmask); 00079 00080 return OK; 00081 }
1.5.5