Lecture Slides

 Chapter 1 Fundamentals of Quantitative Design and Analysis

 Figures from Chapter 1 of the Textbook

 CSE341 Review ISA and Programming

 CSE341 Review Processor Design (Updated to include ILP and more)

  Single-Cycle Example(ppt) (pdf)

  Pipelining Example(ppt) (pdf)

  CSE341 Memory

 Figures from Chapter 2 of the Textbook

  Instruction Level Parallelism (with emphasis on dynamic scheduling, Tomasulo’s examples)

  Chapter 3 (CA-ILP)   Figures from Chapter 3

http://www.cse.buffalo.edu/~rsridhar/courses/cse241/blueball.gif  Chapter 4 (CA-Vector, SIMD, GPU)  Figures from Chapter 4

http://www.cse.buffalo.edu/~rsridhar/courses/cse241/blueball.gif  Chapter 5 (Thread level parallelism)  Figures from Chapter 5

http://www.cse.buffalo.edu/~rsridhar/courses/cse241/blueball.gif  Chapter 6 (Waerhouse-scale computer)  Figures from Chapter 6

http://www.cse.buffalo.edu/~rsridhar/courses/cse241/blueball.gif  Chapter 7 (Domain- Specfific Architectures)  Figures from Chapter 7

  Lecture Verilog

Verilog quick reference manual, IEEE Standard Verilog Manual

MIPS Green Data Sheet

 

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