VLSI Testing
Group
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Zarrineh K., S. Upadhyaya and V. Chickermane,
"System-on-Chip Testability Using LSSD Scan
Structures",
IEEE Design and Test of Computers, Vol. 18, No. 3, May-June 2001, pp. 83-97.
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Nagaraj P., S. Upadhyaya, K. Zarrineh and D. Adams,
"Defect analysis and realistic fault
model extensions for multiport SRAMs",
10th IEEE North Atlantic Test Workshop,
Gloucester, MA, May 2001. |
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Zarrineh K. and S. Upadhyaya,
"Programmable Memory BIST and a New Synthesis Framework",
IEEE 29th International Fault Tolerant Computing Symposium, Madison, WI, pp. 352-355, June 1999.
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Zarrineh K. and S. Upadhyaya,
"A Design Test Perspective on Memory Array Synthesis"
IEEE International Symposium on Circuits and Systems, Orlando, FL, May 1999.
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Zarrineh K. and S. Upadhyaya,
"A New Framework for Automatic Generation, Insertion and Verification of Memory Built-in Self Test Units",
17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999.
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Zarrineh K. and S. Upadhyaya,
"On Programmable Memory Built-in Self Test Architectures",
Design Automation and Test in Europe 99, Munich, Germany, March 1999.
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Zarrineh K., S. Upadhyaya and S. Chakravarty,
"A New Framework for Generation of Optimal March Tests for Memory Arrays",
IEEE International Test Conference, Washington DC., pp. 73-82, October 1998.
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Zarrineh K. and S. Upadhaya,
"A New Approach to Programmable Memory Built-in Self-test Scheme",
IEEE International Workshop on Embedded Fault Tolerant Systems, Boston, MA, pp. 128-133, May 1998. |
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Zarrineh K., S. Updhyaya, P. Shepard III,
"Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips",
16th IEEE VLSI Test Symposium, Monterey, CA, pp. 98-103, April 1998.
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Zarrineh K., S. Updhyaya, P. Shepard III,
"Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips",
16th IEEE VLSI Test Symposium, Monterey, CA, pp. 98-103, April 1998.
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Goldberg S., S. Upadhyaya and W. K. Fuchs,
"Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares",
IEEE Defect and Fault Tolerance Symposium, Boston, MA, pp. 318-326, Nov. 1996.
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Goldberg S., S. Upadhyaya and W. K. Fuchs,
"Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares",
IEEE Defect and Fault Tolerance Symposium, Boston, MA, pp. 318-326, Nov. 1996.
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L. Nachman, K. K. Saluja, S. J. Upadhyaya and R. Reuse, "Random Pattern Testing of Sequential Circuits Revisited",
IEEE Fault Tolerant Computing Symposium, Sendai, Japan, June 1996, also in
IEEE Transactions on Computers, Special Issue on Dependability of Computing Systems, Vol. 47, No. 1, pp. 129-134, January 1998.
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R. Spine and S. J. Upadhyaya,
"Concurrent Test versus Design for Test Resources in Mixed Signal Circuits",
2nd IEEE International Mixed Signal Testing Workshop, Quebec City, Canada, pp. 173-180, May 1996.
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Goldberg S. and S. Upadhyaya,
"Utilizing Spares in Multichip Modules for the Dual Function of Fault Coverage and Fault Diagnosis",
Defect and Fault Tolerance Workshop, Lafayette, LA, pp. 234-242, Nov. 1995.
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