Final Exam Review: Study Material, Topics and Sections

December 3, 2017 by Bina

Final Exam Schedule

Sequential Circuits

1. Chapter 4: Section 4.12 Verilog Description of Combinational circuit
   Verilog (structural) description of gate circuit. Read the secton on writing a test bench.(like hwk8, lab6, but with a test bench. Example: Fifth Edition: p.181 Sixth Edition: p.233-234.)
   
2. Chapter 5: Section 5.5 Analysis of sequential circuits
   Given a cicuit (see fig.5.15) get the state equations, state table, state diagram.
   Here is a sample question and answer.
3. Chapter 5: Section 5.6 Verilog Description of Sequential Circuit
   Behavioral verilog model. Example 5.7 of Fifth Edition: p.215,229; Sixth Edition: p.296,297
   
4. Chapter 5: Section 5.8: Synthesis of sequential circuits
   Synthesis with JK, T and D FF. Problem statement, state diagram, state table, FF input equations, FF diagram.
5. Chapter 7: Section 7.6: Programmable Logic Array
   
6. IEEE-754 Single precision (32-bit) floating point represetation.
   Here is a sample question and answer.

Classnotes

August 30 by Bina

Classnotes

Date	Topic	Chapter	Classnotes
8/28	Course Goals and Plans	Course description
8/30	Number System	Chapter 1	C1
9/1,6	Signed Arithmetic	Chapter 1	C2
9/8	Boolean Algebra	Chapter 2	C3
9/11	Floating Point Representation	Chapter ?	C4
9/13,15	Problem Solving using Logic Gates	Chapter 2	C5
9/18	Karnaugh Map	Chapter 3	C6
9/20	Problem Solving using K-Maps: 7Seg LED display	Chapter 3	C7
9/22,25	Analysis of Logic Circuit; SSI, MSI, LSI	Chapter 4	C8
9/27	MSI: Decoder	Chapter 4	C9
9/29	MSI: Multiplexer	Chapter 4	C10
10/2	MSI: Comparator, Carry Look ahead Adder	Chapter 4	C11
10/6,10/9	REVIEW, In-class REVIEW	Chapter 1-4	C12
10/11	Exam 1	Chapter 1-4	Review
10/13,18	Sequential Circuit Analysis	Chapter 5	C13
10/20-27	Sequential Circuit Synthesis	Chapter 5	C14
11/1	Hardware Description Language: Verilog	Chapter 3-5	C15
11/8	Hardware Description Language: Verilog	Chapter 3-5	C17
11/8	Field Programmable Logic Array	Chapter 7	C18

Number Systems

August 30 by Bina

Consider a pack of playing cards, a set of coins: how do understand these systems? How do you model them so that a computer can understand?
We think in decimal, computers number crunch in binary
How do you define a number system?
Radix of a number system?
Number conversion
Decimal to binary, binary to decimal
Numbers with fractions
ASCII 7-bit code for information representation

Notes

Signed Integer Arithmetic

Sept 1 by Bina

ASCII 7-bit code for representation of characters.. standard code
BCD for binary form of decimal
Representing numbers for efficient computation: 1's complement and 2's complement
In general, lot of research effort on "coding" information for efficient and reliable processing: excess-3 code, Gray code
Binary arithmetic: sign-magnitude vs. 2's complement
Signed Binary Arithmetic Consider numbers A = 53 and B= 76. Assume positive numbers are represented using sign-magnitude and negative numbers as 2's complement. Perform the operations below in binary. Assume 8-bit container. Specify if the result is positive, negative or overflow and explain your answer.

1. X = A + B
2. Y = A - B
3. Z = -A -B
4. W = -A + B

Notes

Boolean Algebra

Sept 8 by Bina

Boolean algebra is like any other math system: Set of elements, set of operators, and a number of axioms and postulates.

Basic operations {AND, OR, NOT} {.,+,'}

Most common postulates:
1. Closure: w.r.t an operator is closed if for every pair of elements of S, the binary operator results in a unique value in the S.
2. Associative: (x*y)*z = x*(y*z)
3. Commutative: x * y = y *x
4. Identity element: e *x = x*e = x where e is the identity element
5. Inverse element: x *x' = 0
We can repeat all these w.r.t to + operator.

Theorems:
x+x = x x*x =x
(x')' = x involution
x + (y + z) = (x+y)+z associative
x*(y + z) = x*y + x*z distributive

De Morgan's law: (x + y)' = x' * y'
x + xy = x Absorption law x (x+y) = x

Operator precedence: (i) parentheses (ii) NOT (iii) AND (iv) OR

Implementation of Boolean functions:
f1 = x + y'z
F2 = x'y'z + x'yz + xy' ---> F2= xy' + x'z

Algebraic simplification: goal is to minimize the Boolean function to minimum number of literals and minimum number of terms. We will use only sum of products form.

F1 = x + xy
F2 = xy + x'z + yz
Minterm --- product term -? canonical form : sum of minterms
Maxterm --- sum term -? canonical form: product of maxterms
Standard forms of Boolean expressions.

Truth table to represent a function.


Goal of simplification is to minimize (i) teh number of terms (ii) minimize number of literals per term.

Number Systems: Floating Point Representation

Sept 11 by Bina

Integer numbers represnt whole numbers. What if we wanted to represent a real number? What if we wanted to represent a very small number or a very large number?
Learning outcome of this lesson:

1. Compare integer and FP representation
2. Describe the IEEE754 format for FP representation
3. Given a real number such as 453.237, write it in IEEE 754 FP format

Problem Solving using Boolean Algebraic Simplification

September 13, 15 by Bina

Lets review what we did last class.
What is simplification of a Boolean expression? Goal of simplification is to minimize the number of literals and also the number of terms in an expression. We will look at algebraic simplification by applying the laws and theorems.

We will implement the Boolean expressions uisng logic gates. {AND, OR, NOT} combiation and also using only NAND gate. We will also implelemt the circuits using common IC chips.

Logic gates are used to implement Boolean functions. For the gates, study it through the name of the gate, logic operator, graphic symbol, truth table and expression representing the operation of a gate.

Boolean Functions

We will discuss implementation of Boolean functions. Here are the steps in the design and implementation of a Boolean function.

1. Problem statement
2. Truth table
3. Sum of minterms expresions
4. Simplification or minimization of the expression
5. Implementation using logic gates

Problem Statement: Design a combinational logic circuit to generate odd parity for the BCD code; a logic circuit that will generate the odd parity bit for any 4-bit combination of the BCD code. Implement it using (i) {AND, OR, NOT} and (iii) using only NAND gates.

What is BCD code? Binary Coded Decimal. It is a 4-bit binaty code representing the decimal digits {0..9}.

Karnaugh Map

September 18 by Bina

We will explore K-maps for 2-3-4-variable functions.

Problem Solving using K-map

September 21 by Bina

Lets review logic gates.

Problem Statement: Design and implement the logic circuit for BCD-7-segment display.

Input: 0,1,2..9

Output: 7-segment display for the input digit.

Analysis of Combinational Circuit; MSI Chips

September 22-29 by Bina

So far we synthesized or designed and constructed circuits. Today we will learn how deconstruct and analyze a combinational circuit. See figure 4.2, p.128. Fifth Edition.

We will discuss SSI, MSI and LSI.
Start looking at MSI chips and design a half-adder.

MSI Chips: 4 bit Comparator & Carry Look Ahead Adder

Oct. 2,4 by Bina

We will learn design and implementation of (i) Comparator (ii) Carry Look-ahead adder. We will also learn an alternative way to implement circuits using only NAND gates.

Introduction to Sequential Circuit

Oct 13 by Bina

We will study sequential circuits using

1. Basic components: Flip-flops (FF)
2. Major elements: memory (FFs) and circuits driving the FFs
3. Analysis of sequential circuit
4. Synthesis of sequential circuits
5. From problem statement to sequential circuit design
6. State diagrams: Finite state machines (FSM) design tool

Exam Analysis

Oct.18 by Bina

Here it is. The question by question analysis of your midterm performance;

Review of Sequential Circuit Analysis and Design

Oct.30by Bina

Characteristic table describes the effect JK on state. State table explain the state transtions from A(t) to A(t+1) and the FF inputs that bring about the change.

Lets work on problem 5.9.

Lets review steps in analysis of sequential circuit (i) analysis (ii) design.

Verilog Hardware Desription Language: Chapter 3

November 1 by Bina

Boolean algebraic simplification is good for explaining the fundamentals; K-map is good for further formalizing the simplification process. However for function with more than 4 variables, these methods DO NOT scale well. We need better ways of decribing the hardware so that the process of implementing (manufacturing) and testing can be scaled up and automated for LSI, VLSI and onwards. Hardware Description Languages (HDL) such as Verilog are solutions that address the scalability and automation issues. We will look at only Verilog. Here is an introductory Presentation on Verilog

Getting Started with Verilog

November 3-8 by Bina

This page provides some useful information about gettign started with verilog.

1. How to access CSE server using Putty
2. How to compile verilog code?
3. Notes from a Ex-UTA for this course: JD's notes
5. Unix Command sheet
6. vim editor commands sheet

4-bit Adder Verilog description with test bench

Adder.v fig329b.v fig329b1.v

Verilog Description of Sequential Circuit

April 17 by Bina

Here is a complete example of a simple 2-bit counter shown in the figure on the right. In this diagram, x is the input for counting and y is the output.

The verilog code for the circuit and the test bench is shown below: and available here.

// Sequential Circuit Example 5_20 : the instantiation is inside
// the test bench
// item 1
module counter2 (output y, input x, input clock,input reset);
// item 2
   reg[1:0] state;  // 2 bits
// item 3
   parameter S0=2'b00, S1 = 2'b01, S2=2'b10, S3=2'b11;
//item 4 when and how do the state transitions happen?
   always@ (posedge clock, negedge reset)// event driven
     if (reset == 0) state <= S0;
     else case (state)
	    S0 : if(x==1) state <= S1; else state<= S0;
            S1 : if(x==1) state <= S2; else state<= S1;
            S2 : if(x == 1) state <= S3; else state<= S2;
            S3 : if(x == 1) state <= S0; else state<= S3;
	  endcase // case(state)
// item 5 : output
   assign    y = (state==S3);
endmodule // counter2

module counter2_tb;
   // stand alone
 // item 1 definitions
   reg x, clk, rst;
   wire y;

 // item 2 instantiate counter2
   counter2 C1(y, x, clk,rst);
 // item 3
   initial #200 $finish; // duration of your simulation testing
// item 4
   initial begin
      rst = 0;
      clk = 0;
      #5 rst = 1;
	  
      repeat (16)
	#5  clk = ~clk;
   end

// item 5 for x
initial begin
 x = 1'b0;
 repeat(8)
 #10 x = ~x;
end
// item 6 for montioring, output text and waveform
initial begin
$monitor("x=   %d  y= %d",x,y);
$dumpfile("example1.vcd");
$dumpvars;
end
endmodule
  

Actual verilog code can be found at example1.v

Commands for compiling and simulating the Verilog code.

iverilog -o example1.vvp example1.v
vvp example1.vvp
gtkwave example1.vcd

Memeory and Programmable Logic: Chapter 7

Nov. 27 (Section 7.6 only) by Bina

How do we scale up and automate the process of synthesis of circuits that we learned so far.
Consider a combinational circits and its block diagram as shown below.

Combinational circuit has n inputs, k outputs. The memory on the right has n bits address and k bits data. Here lies a great idea, a "disruptive" one: Why dont we replace the block of gates with block of memory lcoation and program them with appropriate data. Porgrammable Read Only Memory (PROM) model of programmable logic.

Here is another idea: if we have n variables, the number of minterms is 2^n. These can be formed using 2^n AND gates. If there are k outputs, there are k functions. We can implment the k functions using the minterms we formed earlier and k OR gates. Here is an idea: if we can pre-create the minterms, and allow the OR gates to be programmed,then we have programmable gate array (PGA) and if we can program it "in field" we have field programmable gate array or FPGA

Lets work on a problem to understand the "FPGA" concept.
Example 7.2 from your text book. Implement these function using an FPGA.
F1(A,B,C) = ∑(0,1,2,4)
F2(A,B,C) = ∑(0,5,6,7